I. Field of the Invention
The present invention relates to a device for the protection against breakdown of an N+ type diffused region inserted in a vertical-type semiconductor integrated power structure.
II. Prior Art and other Considerations
A semiconductor integrated structure comprises essentially an N+ type substrate over which there is superimposed an N- type epitaxial layer in which there are obtained P type insulation pockets, connected to ground, which in turn contain respective N type regions.
In a structure of this type the problem often arises of connecting two metal tracks avoiding the crossing with other metal tracks.
According to a first prior art solution technique such problem is solved by inserting N+ type regions inside the N type regions. Such regions behave like low-value resistances and have the function of connection underpasses (also known as crossunders) between the metal tracks.
Often, according to a second prior art solution technique, each of these N+ type connection regions is diffused over a P type region in turn accomplished inside an N type region and having the extremities shortcircuited with those of the N+ region.
If the first technique for solving the problem is used, inside the integrated structure there is the formation of a parasitic transistor whose base is accomplished at the P type insulation pocket, while the collector is accomplished in the N type region and connected to the N+ type region and the emitter is connected to the substrate.
If the second technique for solving the problem is used, inside the integrated structure there is the formation of an SCR parasitic device formed by two transistors, a first of which has the emitter accomplished inside the P type region, the collector accomplished inside the P type insulation pocket and the base accomplished in the N type region, while the second transistor has the collector accomplished in the N region, and thus connected to the base of the first transistor, the base accomplished in the insulation pocket, and thus connected to the collector of the first transistor, and lastly the emitter accomplished in the substrate.
In both techniques for solving the problem during the operation of the circuit the N+ type substrate can go negative with respect to ground. In such a case either the parasitic transistor of the first solution technique or the SCR parasitic of the second solution technique is triggered. If one end of the N+ region connecting the metal tracks is connected to a low impedance power supply unit, the current through the transistor or the SCR are not limited to a practical extent and cause a dissipation of power which damages the connection itself.
If the second solution technique is used a possible protection against parasitic effects may be accomplished by biasing the N region contained in the insulation pocket, through a N+ contact region, at a higher voltage than that attained by the N+ connecting region. In this case the SCR's first parasitic transistor is reverse biased.
If, on the other hand, for circuit reasons, the N+ connection region is also connected to the above higher voltage, and this is also the maximum bias voltage existing in the integrated circuit, the problem arises again triggering the SCR and there is also triggered a further parasitic transistor having the collector accomplished in the N+ contact region, the base accomplished in insulation pocket P and the emitter accomplished in the N+ substrate. There thus occurs the possible damage of the integrated circuit.
The object of the present invention is to create a suitable structure to protect the N+ type crossunder connection regions from possible breakdowns determined by the presence of parasitic transistors.